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Generate FPGA Data Capture Components The signals are a 16-bit 'temperature', and 8-bit 'counter'. The 'temperature' signal is the reading of register 0x00 from XADC, which stores the converted raw temperature sensor. It has 16bits, but only the 12-bit most significant bits (MSB) are the raw temperature sensor reading. In 2003, CU student Nate Seidle fried a power supply in his dorm room and, in lieu of a way to order easy replacements, decided to start his own company.
Active3 years, 4 months ago
I have the following code to try and read the ADT7420 on my nexys4DDR FPGA board. I can't seem to get it to work. All of the led's wind up set to on, and I can't find the problem. Where am I going wrong?
Dillon E.Dillon E.
1 Answer
Looks like you are using
SDI
as a tri-state, however a tri-state must be wire
type; not a reg
. Deliberately assigning x
or z
to a reg
type is an indicator that value under this scenario is a don't care, allowing the synthesizer to drive the resulting net to any value (typically based on logic optimization). It is still driven, not tri-stated.A tri-state should be a
wire
type, and the assignments should be simple:FYI:
Most RTL coding guidelines recommend never assigning a
It sounds like you are directly synthesizing your RTL code without simulating. It is recommended to simulate before synthesizing. It is easier to debug logic issues in simulation.
You may have other issues with your code, but this should be enough to get you in the right direction.
GregGregMost RTL coding guidelines recommend never assigning a
reg
type to x
or z
.It sounds like you are directly synthesizing your RTL code without simulating. It is recommended to simulate before synthesizing. It is easier to debug logic issues in simulation.
You may have other issues with your code, but this should be enough to get you in the right direction.
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